1. Field of the Invention
The present invention relates to an AC plasma display unit and its drive circuit.
2. Description of the Related Art
FIG. 7 shows the structure of a cross section of a pixel 10 in a three-electrode surface-discharge AC plasma display panel (PDP).
A pair of electrodes X1 and Y1 extending in a direction vertical to the paper surface are formed on a glass substrate 11, with a dielectric layer 12 covering it, and an MgO protective film 13 further covering that. An address electrode A1 extending in the left/right direction on the paper surface is formed on a glass substrate 14 which is provided facing opposite the glass substrate 11, with a phosphor 15 covering it. A discharge space 17 located between the MgO protective film 13 and the phosphor 15 is charged with, for instance, Ne+Xe Penning mixed gas.
FIG. 6 shows a schematic structure of a plasma display unit 20.
In a PDP 21, electrodes X1 to Xn, forming pairs with electrodes Y1 to Yn respectively, are provided parallel to one another, and address electrodes A1 to Am are provided intersecting them over a distance, to form m.times.n number of pixels in a matrix. The electrodes X1 to Xn are commonly connected at one end. Hereafter, the electrodes A1 to Am, the electrodes X1 to Xn and the electrodes Y1 to Yn are collectively referred to as electrodes A, electrodes X and electrodes Y respectively.
Voltage with the waveforms shown in FIG. 9 are applied to these electrodes. Voltages Va, Vsc and Vs in FIG. 9 are generated at a power source circuit 22 and are supplied to the electrodes via an address driver 23, a Y-common driver 24A, a scanning driver 25 and an X-common driver 26. In FIG. 6, Vcc is a power source voltage for a logic circuit and Vd is a power source voltage for a drive circuit. For instance, the discharge start voltages between adjacent electrodes X-Y and between electrodes A-Y that face opposite are at 290 V and 180 V respectively, and in this case, the power source voltages are, for instance,
Vs=180 V, Va=50 V, Vsc=100 V Vcc=5 V, Vd=15 V. PA1 Vs=180 V, Va=50 V, -VY=-150 V, -Vsc=-50 V. PA1 a first switching diode (D6) having a cathode connected to the output terminal and an anode connected to the first input terminal; and a second switching diode (D5) having an anode connected to the output terminal and a cathode connected to the second input terminal.
The address driver 23, the Y-common driver 24A, the scanning driver 25 and the X-common driver 26 are controlled by control signals from a control circuit 27. The control circuit 27 generates the control signals using a dot clock CLK, a vertical synchronizing signal VSYNC and a horizontal synchronizing signal HSYNC which are provided from the outside, and converts the display data DATA, provided from the outside, to data for the PDP 21 and provides the converted data to the address driver 23.
The address driver 23 is provided with a shift register 231, a latch circuit 232 and an A-driver 233 with m number of outputs of the A-driver 233 connected to the address electrodes A1 to Am. The A-driver 233 is provided with m number of drivers which are structured identically in correspondence to the address electrodes A1 to Am, and the driver for the address electrode A1 is referred to as an A1-driver 2331. When display data corresponding to one line are transferred serially from the control circuit 27 to the shift register 231, these data are held in the latch circuit 232 and, based upon the output from the latch circuit 232, drive voltages are supplied to the address electrodes A1 to Am via the A-driver 233.
The scanning driver 25 is provided with a shift register 251 and a Y-driver 252. The Y-driver 252 is provided with n number of drivers structured identically and the driver for the electrode Y1 is referred to as a Y1-driver 2521. The outputs of these n number of drivers are connected to the electrodes Y1 to Yn. During an address period, "1" is supplied to the series data input of the shift register 251 only during the initial address cycle, and this is then shifted in synchronization with the address cycle so that electrodes Y1 to Yn are selected sequentially.
FIG. 8 shows a schematic structure of the drive circuit for the pixels 10. In FIG. 8, the drive circuit required during a reset period in which the wall charge for all the pixels is cleared, is omitted.
In FIG. 8, SW1 to SW15 are switch elements, D1 to D15 are diodes, L1 to L3 are coils and C1 and C2 are capacitors for power recovery.
The A1-driver 331 is a push/pull type, and when the first bit of the latch circuit 232 (see FIG. 6) is at "1", the switch SW2 is turned off and the switch SW1 is turned on so that a write voltage Va is supplied to the address electrode A1, whereas when the first bit of the latch circuit 232 is at "0", the switch SW1 is turned off and the switch SW2 is turned on so that 0 V is supplied to the address electrode A1.
The X-common driver 26 is provided with an X-sustaining voltage circuit 261 which is structured similarly to the A1-driver 233, and a power recovery circuit 262.
During a sustain period in FIG. 9, in a state in which the switches SW3 and SW4 are turned off and the voltage at the electrodes X is at 0 V, the switch SW12 is turned on first in order to start a sustaining pulse Ps, and then the charge accumulated in the capacitor C1 is supplied to the electrodes X through the diodes D12 and the coil L1. When the voltage at electrodes X rises to near the level of the sustaining voltage Vs, the switch SW3 is turned on to raise the voltage at the electrodes X up to the sustaining voltage Vs. The wall voltage is added to this voltage, then a sustaining discharge is generated and a wall charge with reverse polarity is collected on the MgO protective film 13. Then the switches SW12 and SW3 are turned off in that order.
The switch SW13 is turned on to cause the sustaining pulse Ps to fall and the electrical charge on the electrodes X is recovered in the capacitor C1 via the coil L1, the diode D13 and the switch SW13. When the voltage at the electrodes X falls to near 0 V, the switch SW4 is turned on so that the voltage at the electrodes X is brought down to 0 V. Then the switches SW13 and SW4 are turned off in that order.
The Y1-driver 2521 has a structure that is similar to that of the A1-driver 2331 and the X-sustaining voltage circuit 261.
The n number of drivers of the Y-driver 252 are connected in parallel to one another via lines SU and SD and the Y-common driver 24A is connected to these lines SU and SD to constitute a common circuit for the electrodes Y1 to Yn. The Y-common driver 24A is provided with a scanning voltage circuit 241A, a Y-sustaining voltage circuit 242A and a power recovery circuit 243A.
During an address period in FIG. 9, first, only the switches SW5, SW7 and SW8 among the switches SW5 to SW10, SW14 and SW15 are turned on, an unselected voltage Vsc is applied to the line SD and electrode Y1 and a selected voltage 0 V is applied to the line SU and then the switch SW5 is turned off to enable start of scanning. In this state, the switch SW6 is turned on and the selected voltage 0 V is applied to the electrode Y1. At this time, a primary discharge is performed between the electrode Y1 and selected address electrodes among the address electrodes A1 to an in correspondence to the display data, and triggered by this discharge, a discharge occurs between the electrodes X-Y so that the wall charge required for a sustaining discharge is accumulated on the MgO protective film 13. Then the switch SW6 is turned off and the switch SW5 is turned on to apply the unselected voltage Vsc to the electrode Y1. Subsequently, identical control is performed for the remaining n-1 number of drivers of the Y-driver 252 sequentially. In FIG. 9, Psc indicates the scanning pulse.
During a sustain period shown in FIG. 9, first, only the switch SW15 among the switches SW5 to SW10 and SW14 and SW15 is turned on, and the electrical charge accumulated in the capacitor C2 is supplied to the electrodes Y via the switch SW15, the diode D15, the coil L3 and the diode D6. Then, when the voltage at the electrodes Y rises to near the sustaining voltage Vs, the switch SW10 is turned on to raise the voltage at the electrodes Y up to the sustaining voltage Vs. A sustaining discharge occurs between the electrodes X-Y, where the sum of the sustaining voltage Vs and the wall voltage exceeds the discharge start voltage and a wall charge with reverse polarity is accumulated on the MgO protective film 13. Following this, the switches SW15 and SW10 are turned off in that order. Then, the switch SW14 is turned on, the electrical charge in the electrodes Y is recovered in the capacitor C2 via the diode D5, the coil L2, the diode D14 and the switch SW14. When the voltage at the electrodes Y falls to near 0 V, the switch SW9 is turned on so that the voltage at the Y electrodes is lowered down to 0 V. Then the switches SW14 and SW9 are turned off in that order.
With the waveforms of the voltages applied to the electrodes as shown in FIG. 11, during an address period, a reduction in power consumption is achieved by reducing the write voltage Va applied to the address electrodes A1 to An where the number of pulses is high, with the unselected voltage and the selected voltage at the electrodes Y1 to Yn being -Vsc and -VY respectively. A drive circuit that achieves this is shown in FIG. 10, in correspondence to the circuit shown in FIG. 8. The power source voltages are, for instance,
At the Y-common driver 24A in FIG. 8 and the Y-common driver 24B in FIG. 10, since the discharge current for many pixels flows through the lines SD and SU during a sustain period, the impedance must be reduced by making these lines wide. Since there are two wide lines between the Y-sustaining voltage circuit 242A and the scanning voltage circuit 241 or 241A, the switch SW9 and the diode D9 must be connected to the line SD and the switch SW10 and the diode D10 must be connected to the line SU which is away from the line SD, and the diodes D9 and D10 are independent of the switches SW9 and SW10, the structure becomes complex, preventing higher integration of the driver and cost reduction.
Normally, power MOS transistors are used for switches. However, since a voltage at Vs+VY=330 V is applied to the switch SW6 in FIG. 10, when the switch SW10 is turned on, necessitating a switch to be employed for the switch SW6 with a high voltage standing, higher integration of the driver and cost reduction are prevented.